1. Field of the Invention
The invention generally relates to bus systems for transmitting information and, in particular, to a wired-OR bus system having multiple-driver signal lines.
2. Description of Related Art
Bus systems are commonly used for transmitting information between devices within a computer system or similar systems. Within a computer system, individual devices which transmit information over the bus may include, for example, one or more microprocessors, dynamic random access memory chips (DRAM), I/O bridges and the like. For generality and clarity, any of the various devices connected to a bus will be referred to herein merely as bus agents, unless otherwise noted.
It is desirable to transmit information from one bus agent to another as quickly as possible. The rate by which information signals may be transmitted on a bus is fundamentally limited by the electrical or physical characteristics of the bus as well as by other factors. For example, the rate of information transmission is fundamentally limited by the propagation time T required to transmit a signal from a driver on the bus to a receiver on the bus. If a signal can be observed within one propagation delay time T by every observer agent on the bus, the bus system is capable of "incident wave switching", which represents a desirable high transmission rate. However, other electrical limitations can prevent a bus system from employing incident wave switching. One such limitation is that signal transitions on the bus from one voltage level to another require a minimum period of time to settle. Typically, a sharp transition is followed by a set of voltage swings or oscillations. The voltage swings following a sharp transition are often sufficient to swing the voltage past the threshold voltage. Accordingly, agents connected to the bus must be capable of distinguishing between intended voltage transitions and voltage swings occurring before the voltage level adequately settles. If the voltage oscillations fall below the threshold it may prevent a receiver on the bus from being able to detect a signal within the time required by incident wave switching.
The foregoing problem is typically solved merely by defining a clock signal which has a period longer than the settling time for the voltage transitions. All intended transitions are required to be asserted onto the bus at one of the low to high transitions of the clock signal so that agents observing signal transitions can observe those transitions the next low to high transition of the clock. By choosing a sufficiently long clock period, it can be guaranteed that a signal transition is adequately stabilized so that it is observed by the receivers. Typically, the clock period is set to 2T+k, where k is a constant related to output buffer delays, clock to output gate delays, input buffer delays and input set-up times. However, the foregoing solution is only effective in bus systems wherein only a single bus agent is allowed to assert signals onto a bus line at any given time. Other bus systems allow two or more bus agents to assert signals onto a single line simultaneously. An example of such a bus system is a wired-OR bus system employing Gunning transceiver logic (GTL). In a wired-OR system, an active signal is defined as a low voltage level on a signal line. Each bus agent includes a wired-OR bus driver which is capable of asserting an active signal onto the bus line by pulling down the voltage onto the bus line. In this manner, any single agent or any number of agents can assert an active signal onto the line by merely pulling the voltage down to a low voltage level. Each bus agent also includes a wired-OR bus receiver which detects the voltage level on the signal line. The signal detected by the wired-OR receiver effectively represents the OR-combination of signals asserted by all of the bus agents, hence the name wired-OR.
Sharp signal transitions on a wired-OR bus result in voltage swings, as described above. However, in a wired-OR bus, voltage swings may occur even under circumstances wherein no voltage transition is intended. This problem is generally referred to as the "wired-OR glitch" and it imposes a further constraint on the ultimate speed of data transition, which may not be present in a non-wired-OR bus system. The wired-OR glitch occurs if several bus agents assert a low to high signal transition simultaneously while additional bus drivers continue to drive a low voltage level. Since at least some of the bus agents continue to drive the bus low, the state of the bus should remain low and no threshold voltage transitions should occur. Nevertheless, as a result of the fact that some of the agents are attempting to assert a low to high transition by releasing the signal line, a set of significant voltage swings occur which could be misinterpreted as an intended voltage level transition. In other words, even though the signal level is intended to remain low and even though at least some of the agents continue to pull down the voltage to a low level, anomalous low to high and high to low voltage transitions can nevertheless occur, causing a wrong interpretation by some of the receivers.
One solution to the wired-OR glitch problem is to simply limit, by protocol, that no two bus agents can assert signals at the same time on the wired-OR signal line. A signal line wherein only a single bus driver can assert a signal at any particular time is referred to as a single driver bus line. Although the foregoing eliminates any wired-OR glitch problem, a single driver signal line is incapable of benefiting from the advantages of wired-OR technology which inherently allow for multiple bus agents to drive signals at the same time. To allow multiple drivers and to avoid signal settling problems, the clock rate is typically set to be sufficiently slow to allow for the wired-OR glitch oscillations, and other oscillations, to decay before any additional signals are asserted. Typically, the clock period is set to be at least equal to 2T+k. However, such results in a substantially slower clock rate than can be employed on single driver signal lines and does not meet the criterion for incident wave switching.
It would be desirable to provide a method and apparatus for transmitting signals on a wired-OR bus line which allows for multiple bus drivers to assert signals simultaneously while also employing a clock period smaller than 2T+k and meeting the criterion for incident wave switching. It is to this end that aspects of the present invention are drawn.